| 摘要 |
<p>PURPOSE:To facilitate the margin test of a synchronizing clock signal by outputting the clock signal of an oscillator selected based on the select condition signal from a control circuit. CONSTITUTION:A reset signal is outputted from an indicating part 10 by power-on to initialize a count register 8 and a clock control part 9. A clock selector 6 selects a first oscillator 1 and suppresses the operation of a frequency dividing circuit 5. When a start signal is outputted from the indicating part 10, the circuit 5 is started, and the synchronizing clock having a frequency based on the oscillator 1 is outputted and is inputted to a data processing circuit part. Then, an initial diagnostic program (PG) of a data processor based on a normal clock frequency is executed. When this PG is terminated, a stop signal is outputted from the indicating part 10, and the register 8 is counted up, and the selector 6 selects a second oscillator 2, and a diagnostic PG based on the clock frequency of this oscillator is executed. This operation is repeated to successively select oscillators 1 to 4, thus executing initial diagnosis and diagnostic PGs.</p> |
