| 摘要 |
PURPOSE:To increase an allowable phase difference approximately double in a transmission system between a raster phase synchronizer and a video signal generator and to transmit a high speed clock signal by reducing the frequency of the clock signal by one half so that the deviation of a phase difference can be ignored. CONSTITUTION:A BDT input signal is input to the CLR terminal of a frequency divider 18, a clock output signal of the output of the frequency divider 18 becomes a L level while the BDT input signal remains a L level, the frequency divider 18 starts operating at the fall of an initial fS (basic clock) signal from the time when the BDT input signal is varied to a H level, and a clock output signal in which the fS signal is divided in frequency by two is formed. This frequency-divided clock output signal is input to the CLK (clock input) terminal of a flip-flop 19, the BDT signal connected to the D (data) input terminal is sampled, and a BDT output signal in which the phase difference between the clock output signal and the BDT output signal is eliminated is formed. |
