| 摘要 |
PURPOSE:To improve the variable range of a delay time by comparing a signal integrating a digital signal and a signal obtained by means of amplitude- amplifying, amplitude-attenuating or amplitude-limiting the digital signal, changing the logical state of an output signal in correspondence with the size relation of both. CONSTITUTION:When the clock pulse signal CL of a square wave is inputted to a low pass filter 1, a triangle wave is inputted to the minus terminal of a comparator 2. The amplitude amplifier signal of the clock pulse signal CL of an intermediate value which is equivalent to the intermediate value of the triangle wave is inputted to the plus terminal of the comparator 2. The output signal of the comparator 2 is equivalent to a signal obtained by delaying the rising timing of the clock pulse signal CL by a prescribed time, and the delay time is the total of a time when the output voltage of the low pass filter 1 takes from a minimum value to a maximum value, and a time when the output voltage takes from the maximum value to below the voltage of the plus terminal. Thus, the variable range of the delay time can be improved since the duty rate of the clock pulse signal does not change even if the delay time is changed. |
