| 摘要 |
<p>PURPOSE:To avoid a decline in the performance of the subject system due to a heavy memory access traffic by dispersing data memories in the unit of processing element (PE) or PE group and, at the same time, making an arbitrary dispersed memory accessible from an arbitrary PE. CONSTITUTION:The whole body of this data flow processor is constituted of two processor groups, one of which is constituted of two PEs 30 and 31 and one data memory 32 and the other of which is constituted of two PEs 34 and 35 and one data memory 36. The memories of the processor are dispersed in such way and, when direct access to one of the memories is not possible, an instruction is transferred to one PE which can make direct access to the memory after the instruction is disintegrated into plural packets. Upon receiving the instruction, the PE makes the memory access and returns results to a designated PE. Therefore, a decline in the performance of the system caused by a heavy memory access traffic can be prevented.</p> |
