| 摘要 |
PURPOSE: To perform the high-level parallel processing with minimum price, size, and complication by sharing a program memory and a program sequence unit including their bus structures by a processor unit and data memories. CONSTITUTION: A processor unit 206 is connected to one of data memories 229 to 231 and a program memory 200 and receives the program instruction which is read from the program memory 200 by a program sequence unit 201. Operations for this data in data memories 229 to 231 are executed in response to this received program instruction. That is, instructions stored in the program memory 200 are executed so as to execute the parallel data processing function for individual sets of data stored in data memories 229 to 231. Thus, the high- level parallel processing is realized without increasing hardware neither the cost. |
