发明名称 PROCESSOR AND ITS DRAWBACK AND RETURN METHOD
摘要 PURPOSE:To shorten the execution time of a drawback instruction by executing the drawback instruction after waiting for the end of the processing, when the drawback instruction is received in the course of processing an instruction whose execution time is short. CONSTITUTION:A microcomputer system is provided with two arithmetic circuits of a CPU (Central Processing Unit) 100 and a FPU (Floatingpoint Processing Unit) 101 in order to execute floating point arithmetic. In such a state, by dividing into an instruction whose execution time is long and an instruction whose execution time is short without executing a drawback instruction by always interrupting a processing by an instruction which is being executed, whether the execution of the drawback instruction is started by interrupting the processing, or the execution of the drawback instruction is started after waiting for the end of the processing executed by the instruction which is being executed is selected. In such a way, the execution time of the drawback instruction of the processor can be shortened.
申请公布号 JPH02148164(A) 申请公布日期 1990.06.07
申请号 JP19880300575 申请日期 1988.11.30
申请人 HITACHI LTD 发明人 OBA MAMORU;MORINAGA SHIGEKI;WATABE MITSURU;KIDA HIROYUKI
分类号 G06F9/30;G06F9/38;G06F9/46;G06F11/28;G06F15/16;G06F15/177 主分类号 G06F9/30
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