| 摘要 |
PURPOSE:To simplify the process of manufacture by making only one layer including a bit line shared by every layer formed of a work line and a memory cell. CONSTITUTION:n layers each formed of a plurality of memory cells 3 respectively connected to a plurality of word lines 5 are laminated, and one layer of a plurality of bit lines 4 is provided on the top. The gate of a NMOS transistor 1 of cells 3 of each layer is connected with the line 5 of each layer, the source is connected with one end of an electrostatic capacity 2 of each layer, and the drain is connected with the line 4 of the uppermost part. The cells of each layer are commonly, i.e., perpendicularly connected to the line 4. Another one end of the capacity 2 is connected to counterpolar terminal commonly to all the cells 3. Thus, an increase in wirings due to the multilayer of a memory cell array can be suppressed to minimum, and problems of flattening due to the multilayer, low temperature of a process, etc., can be eliminated. |
