| 摘要 |
A multi-place ripple-carry adder adapted for CMOS technology incorporates two types of adder cells in which the adder cells of a first type receive two operand inputs and an inverted carry input signal and produce outputs corresponding to a sum signal and a non-inverted carry output signal. The adder cells of the second type accept two operand inputs and produce, as outputs, a sum signal and a non-inverted carry output signal. The gate arrangements of the adder cells of each type are designed so that the capacitance of the carry output is charged through either one transfer transistor acting as a transfer gate, or through a series connection of two transistors of which one transistor acts as a transfer gate. Both binary values can be transmitted as inverted and non-inverted carry output signals without additional threshold voltage losses. The transfer transistors in the carry propagation path are not component parts of a combination gate within the gate arrangement, so that they can be designed with lower impedance than the remaining transistors, resulting in faster rise times for the output pulses.
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