| 摘要 |
An economical circuit arrangement permits disruption, during a nuclear event or single event upset, of operation in portions of a bubble memory system and in a computer connected thereto while maintaining integrity of data stored in the bubble memory. Only critical portions of the bubble support circuits are radiation hardened, and a nonstop logic circuit is provided to continue operation during a nuclear event and to conclude any memory access cycles already in progress at the beginning of the event. Spurious (ionization induced) drive pulses are distinguished from actual pulses. A nuclear event detector generates an output pulse during the event and a delay is provided in a path of the pulses in the critical circuit portions. The delay is greater than the duration of the output pulse of the detector so that pulses arriving after the detector pulse are ignored.
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