| 摘要 |
A semiconductor memory device for reading stored data from a selected memory cell in the semiconductor device to a sensing amplifier. An array of memory cells is arranged in a matrix, each memory cell including a MOS transistor. Word lines are organized to select groups of the MOS transistors. A plurality of first bit lines are arrayed in a matrix with the word lines. The word lines and bit lines together select the selected memory cell from the array. Each first bit line is coupled to either the source electrode or drain electrode of a plurality of MOS transistors. There is at least one second bit line. Each second bit line is selectively coupled to at least two corresponding first bit lines. A first bit line selection circuit selectively couples one of the first bit lines to a corresponding second bit line. A first power source line is coupled to the other of the source and drain of the array of the MOS transistors. A second bit line select means selectively couples a second bit line to the sensing amplifier.
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