| 摘要 |
A novel logic gate, using Gallium-Arsenide technology, that is compatible with TTL or CMOS logic. This logic gate operates off a single voltage supply (e.g. 5 volts) and implements complex logic functions within a single logic gate, such as "AND-OR-INVERT". This is accomplished by having at least one FET with the gate terminal coupling to a current limiter, a first source/drain terminal coupling to the input of a logic sub-circuit, such as a DCFL circuit, and a second source/drain terminal coupling to the input of the logic gate. A diode disposed between the first source/drain terminal and the input to the logic sub-circuit sets the switching voltage of the logic gate. Parallel-connected FETs performs the logical "AND" sub-function while the logic sub-circuit performs the logical "OR" and "INVERT" sub-functions. Also disclosed is a buffer circuit for driving large loads while providing large output voltage swings.
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