Circuit for obtaining a bit-rate clock signal from a serial digital data signal

摘要

To the phase locked loop for controlling the oscillator that regenerates a bit-rate clock signal from a data signal by means of a phase comparison circuit followed by a low pass filter, the output of which controls the oscillator frequency, a digital frequency comparison circuit is provided for assuring that the oscillator frequency will be brought into the capture range of the phase locked loop. The output of the digital frequency comparison circuit is converted from digital to analog form for being used in combination with the low pass filter output to control the oscillator. Frequency and phase control signals are applied to opposite electrodes of a variable capacitance diode in the frequency determining circuit of the oscillator. In order to improve the operation the frequency comparison circuit, delayed and undelayed oscillator output clock signals are sampled by transitions of the data signal for respectively incrementing or decrementing a counter, the state of which is then converted into an anlog signal for contributing to the control of the oscillator. The data signal also is provided in delayed and undelayed forms, and these are combined in an exclusive-OR gate, the output of which is used both in the phase comparison circuit and in the sampling portion the frequency comparison circuit. That portion of the frequency comparison circuit controls a pair of monoflops through D-flipflops so as to provide the necessary incrementing or decrementing pulses for the counter.