RESET CIRCUIT DEVICE

摘要

PURPOSE:To realize the test of an integrated circuit with the optimum time by releasing the reset state of a CPU synchronously with the external reset release signal with no pass through a reset release delay circuit as necessary. CONSTITUTION:The reset release signal is supplied to an external reset terminal 1 and the reset release switch signal is supplied via a reset release switch terminal 11. Thus a line 14 which transmits the reset delay release signal is cut off by a reset signal selection circuit 15. When a line 13 which transmits the reset release signal synchronous with the external release signal conducts via the circuit 15. The selected reset release signal is transmitted to a line 16 to release the reset state of a CPU 5. Thus the CPU 5 starts its working. Thus it is decided whether the reset release signal should be transmitted through a reset release delay circuit 3 or not in accordance with supply or no supply of the reset release switch signal to the circuit 15.