| 摘要 |
PURPOSE:To prevent the generation of a first error exceeding a correctable bit number while combining a software error due to an alpha-ray and an error due to the malfunction of a hardware by prohibiting the access of a memory area when the generation frequency of a second error within the range of the correctable bit number exceeds a specific value. CONSTITUTION:When an interruption is generated in a CPU 7, the CPU 7 reads out the content of an error information holding flip-flop 3 and an error address holding flip-flop 4. When an interruption due to a second error (CE) is generated at a specific frequency or above on the same bit of a same address, the memory area of the address is considered to be malfunctioned in its hardware, and thereafter, the CPU 7 is allowed not the make access to the memory area. Thus, when a first error (UCE) is generated, the operation of the CPU 7 can be guaranteed. |
