| 摘要 |
PURPOSE:To ensure the operation of a CPU by setting variable the release timing of the abnormal stopping state of the CPU. CONSTITUTION:A counter circuit 103 sets the abnormal stopping release timing of a CPU 101 with counting a clock signal. Namely, the release timing of the abnormal stopping of the CPU 101 is set variable by converting the frequency of the clock signal through a second reference clock frequency conversion circuit 120. Thus, even when a noise is generated during communication between the CPU 101 and an external equipment and the CPU 101 continues the stopping state, the stopping state of the CPU 101 can be released after a prescribed time, and simultaneously a correspondence with the CPU 101 of which processing speed is different can be executed. |
