发明名称 SEMICONDUCTOR DEVICE
摘要 PURPOSE:To reduce source resistance by arranging a gate electrode on the uppermost layer of a multi-growth layer, and separately arranging a source electrode and a drain electrode on a high impurity concentration region buried in a region reaching a two-dimensional electron gas layer. CONSTITUTION:A 2DEG (two-dimensional electron)-FET is composed of a GaAs substrate 1, a multi-layer growth layer 2, etc. The layer 2 is formed on the main surface of the substrate 1 by MBE method, as follows; an undoped GaAs layer (buffer layer) 3, an undoped GaAlAs layer (spacer) 4, an n<+> type GaAlAs layer (electron supplying layer) 5 in which high concentration impurity is added, and an undoped GaAlAs layer 6 are deposited, and a hetero-junction is formed by using GaAs and GaAlAs. A two-dimensional electron gas layer 8 generates in the surface layer part of the layer 3. A part of the layer 2 is eliminated as far as the midway depth of the layer 3, and turns to an n<+> type GaAs layer (high impurity concentration region) 15, 16, on which a source electrode 10 and a drain electrode 11 are arranged. A gate electrode 9 is formed on the layer 6.
申请公布号 JPH02143432(A) 申请公布日期 1990.06.01
申请号 JP19880295936 申请日期 1988.11.25
申请人 HITACHI LTD 发明人 MIYASHITA ISAO;SHIMIZU SHUICHI
分类号 H01L29/812;H01L21/338;H01L29/778 主分类号 H01L29/812
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