| 摘要 |
Computer comprising an integrated circuit 11 for input/output management with an input/output 12 connected a data bus 15 to which read-only 20 and random-access 21 memories are linked. The memories 20, 21 are connected directly to the bus, doing away with a buffer between these memories and the corresponding input/output 12. The capacitive load of the bus presented by the wire of the latter and by the memories is of the order of 150 picofarads. <IMAGE>
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