| 摘要 |
PURPOSE:To improve the yield of a DRAM by arranging an adress changeover circuit on the pre-stage or post-stage of an adress buffer of the DRAM, and arranging a data changeover circuit on the pre-stage or the post stage of a data input-output circuit. CONSTITUTION:An adress changeover circuit CAX is arranged on the post stage of a column adress buffer CAB; specified bits of formed complementary inner adress signal are replaced and transmitted; in the same manner, a row adress changeover circuit RAX is arranged on the post-stage of a row adress buffer RAB. The CAX and the RAX contain fuses F3, F4 and fuses F1, F2; the fuses F3, F4 designate bits to be replaced of the complementary inner adress signal: the fuses F1, F2 fix the most significant bit of the complementary adress signal at '0' or '1' before replacement. By this constitution, a usable storage region is partially utilized at the time of obstacle generation; said region can be replaced with a specified adress space and made common. As a result, the manufacturing yield of a DRAM can be improved, and the manufacturing cost can be reduced. |
