发明名称 |
Phase-locked loop circuit |
摘要 |
A phase-locked loop circuit (PLL) to which a phase-synchronization signal is intermittently supplied, both of the natural angular frequency of the PLL and the damping factor of the same are so determined as to prevent a phase difference produced at the next sampling point from exceeding the linear property range of a phase comparator even when the extraneous electrical disturbance enters the PLL. In addition, when the level of a clock control signal supplied to a variable frequency oscillator which varies the clock signal of the PLL in phase and frequency exceeds a predetermined value, the level of the clock control signal is limited to the predetermined value. As a result, it is possible to prevent the output signal of the phase difference from having any discontinuity.
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申请公布号 |
US4929917(A) |
申请公布日期 |
1990.05.29 |
申请号 |
US19880288575 |
申请日期 |
1988.12.22 |
申请人 |
PIONEER ELECTRONIC CORPORATION |
发明人 |
YOKOGAWA, FUMIHIKO;NAITO, RYUICHI |
分类号 |
G11B7/005;G11B20/14;H03L7/00;H03L7/089;H03L7/093;H03L7/10;H03L7/14 |
主分类号 |
G11B7/005 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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