| 摘要 |
<p>PURPOSE:To reduce a synchronizing lock time by adding a detection circuit detecting 0s of (PN pattern stage number + 1) bits and shifting a shift register by an output of the detection circuit. CONSTITUTION:A data of a digital control line (DSC data) is inputted to a shift register 2 and its output is fed to a PM pattern comparison circuit 5A and a circuit 6A for detecting 0s of (PN pattern stage number + 1) sets via a FF circuit 3. A clock having an equal speed as that of a DSC data is inputted to a frequency divider 1A, and the clock is used as the clock being the result of frequency division of one over bit number in 1S frame of the DSC. The PN pattern is generated from a PN generator 4 synchronously with the clock, inputted to the circuit 5A, in which the synchronization is compared and discriminated. Then the output of the circuit 6A is given to an OR circuit 7, from which a shift signal is sent to the register 2. in the normal state of the DSC, each bit is all 0, and since 0s are not consecutive for 0s of (PN pattern stage number + 1), it is utilized.</p> |
