| 摘要 |
PURPOSE:To quicken the leading time of reception by sampling and holding a DC component included in a demodulation signal for a period of preamble signal for bit synchronization included in the reception signal and subtracting the DC component when the transmission data is demodulated. CONSTITUTION:An input signal is converted into an intermediate frequency signal and inputted to a discriminator circuit 4, and angular modulation is applied for demodulation with a transmission data and the demodulation signal is inputted to a low pass filter 5 and inputted to a squelch circuit 10. Since the demodulation signal includes a preamble signal prior to the transmission data, it is detected by the circuit 10 and inputted to a Schmitt trigger circuit 11, from which a pulse signal is obtained. Moreover, the demodulation signal subject to noise elimination is given to a low pass filter 6 to extract the DC component in the preamble period, the result is in holding by a sample-and-hold circuit 12 and the DC component is eliminated by a subtraction circuit 7 while the reception signal exists. |
