Process for fabricating bipolar and CMOS transistors on a common substrate.

摘要

An intercontact dielectric layer includes an underlying layer of undoped silicon dicxide overlaid by a relatively thicker layer of boron- and phosphorus-doped silicon dioxide. The difference in etching rates between the doped and undoped layers allows the use of both wet and dry etches to form contact openings having improved cross-sectional profiles to enhance step coverage of subsequently formed layers.