| 摘要 |
<p>Multiprocessor system having global data replicated in all local memories, each one related to one of the system central processing units (CPUs) where consistency of the global data in each of the local memories is provided by a global write procedure according to which an agent CPUZ, willing to modify a global data in its own local memory, outputs a write command on the system bus for performing the write operation in the local memory of another destination CPU of the system and charcterizes such command as a global write, so that all the CPUs connected to the system bus (including CPUZ) detect such command, perform such write operation in their related local memory, and provide the destination CPU with a signal indicative of performed write operation, so that the destination CPU may signal to CPUZ the execution of the global write. By this procedure it is possible to use a standard system bus and inteface circuits available on the market, such as the coprocessors INTEL MPC, which require, for correct execution of the system bus protocol, the activation of both a requesting coprocessor and a replier coprocessor.</p> |
