Data processing system capable of performing vector/matrix processing and arithmetic processing unit incorporated therein.

摘要

For speed-up of an arithmetic operation on vectors, matrices or a vector and a matrix, an arithmetic processing unit (2) provided in association with a central processing unit has a program memory (8) for storing a microprogram corresponding to a macro-instruction code representative of the arithmetic operation and fed from the central processing unit, and operands codes are transferred from an internal resistor array (16) to operand registors (RG1 to RG4) assigned to an augend and an addend or a multiplicand and a multiplier for calculation carried out by an arithmetic and logic unit (18), wherein the operand codes for the arithmetic operation are successively transferred to the internal resistor array prior to the execution of the micro-instruction codes, so that the arithmetic processing unit completes the task without any interrupt for receiving operands.