Multiple posting cache memory.

摘要

A computer has multiple posting circuits (34) for improving the speed at which the CPU (10) writes to various memory locations. One such posting circuit (23) is associated with the memory controller (22) and another posting circuit (25) is associated with the bus controller (24). A plurality of devices (28-32) are connected to the bus controller (24) over a device bus (26). A cache memory (18) increases the speed of reads from a predetermined range of memory addresses.