| 摘要 |
<p>PURPOSE:To reduce the clock skew and to improve the performance of an LSI by outputting a clock distribution logic to distribute clock signals to FF groups with each area as the unit. CONSTITUTION:A clock distributing circuit consists of a CSP (clock shaper) 200, a fan out adjusting circuit 201, and FFs 204. FFs 204 use clock signals having a clock phase TO and are equally divided to six areas. A clock signal TO-P/N before waveform shaping which has the clock phase TO is inputted to the CSP 200, and the CSP 200 outputs clock signals TO0-P/N and TO1-P/N to TO5-P/N after waveform shaping. The clock signal TO0-P/N is distributed to FFs in the area 1, and the clock signal TO5-P/N is distributed to FFs in the area 6. Thus, the clock distributing circuit of small clock skew is produced in accordance with external specifications of the clock distributing circuit.</p> |
