| 摘要 |
PURPOSE:To input data and a clock into the data discrimination circuit of a data demodulation circuit at an optimum timing by inputting a reference signal in accordance with the transfer speed of a disk device and controlling the delaying time of a delaying circuit. CONSTITUTION:PLL (Phase Locked Loop) circuits 2-4 to generate a first signal synchronizing with read data, a delaying circuit 5 to make the read data into a second signal with delaying for a prescribed time, and a data discrimination circuit 7 to discriminate the data signal and the clock signal being contained in the read data from the first signal and the second signal are provided. When the transfer speed of the disk device is changed, the reference signal corresponding to the transfer speed is inputted and the time of the delaying circuit 5 is controlled. Thus, the data and the clock of the data discrimination circuit 7 can be inputted at the optimum timing. |
