发明名称 CHROMINANCE SIGNAL PROCESSING CIRCUIT
摘要 <p>PURPOSE:To reduce the effect of noise or the like by averaging relating data so as to form data representing 2 periods. CONSTITUTION:A 4fsc clock signal is fed to an A/D converter, in which sampling and A/D corlversion are applied. Then data DP+6(c), DP+2(g) are inverted and DP+4(e), DP(i) are added by an adder means 11 as they are. Then the result of addition is decreased to 1/4 to obtain an average value of 4 data. Then a 1st latch pulse (k) and the 2nd latch pulse (l) are generated from the 4fsc clock signal and an output is obtained from an output terminal 18. The output is similar to that of a conventional circuit in the representation of the fsc 2 periods of a modulated color signal by 2 data and since a mean value of plural values is used, the effect of noise on a modulated color signal is reduced.</p>
申请公布号 JPH02131693(A) 申请公布日期 1990.05.21
申请号 JP19880286055 申请日期 1988.11.11
申请人 SANYO ELECTRIC CO LTD 发明人 YAMAMOTO TORU
分类号 H04N9/74;H04N11/04 主分类号 H04N9/74
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