发明名称 MEMORY CIRCUIT
摘要 PURPOSE: To make it possible to rapidly read and to prevent an effect of a read disturbance by connecting a bus device to a permission line, a bus/ separation device to a memory cell and a driver connected between a read line and a reference voltage to a control node. CONSTITUTION: A read bit line RBL 18 is precharged for reading out a zero level stored in a storage 10. When a zero is stored in the device 10, an internal node 29 becomes an H, and the internal node 25 becomes an L. The read of the zero data is started by a signal sent to a gate of a transistor 52 through a read word line WRL 22. Since the node 29 is the H, the transistor 50 is conducted also, and current routes facing to the RBL line 18, the control node 45 and the base of the transistor 54 are established. Since the transistor 56 is turned on, the collector voltage of the transistor 54 is lowered to a ground level, and the voltage of the line 18 is lowered rapidly, and a sense amplifier detects that to interpret it as that the zero is read out from the memory cell 10.
申请公布号 JPH02130795(A) 申请公布日期 1990.05.18
申请号 JP19890242396 申请日期 1989.09.20
申请人 INTERNATL BUSINESS MACH CORP <IBM> 发明人 JIEEMUZU UIRIAMU DOOSON;PANAGIOTEISU ANDORIYUU FUIRITSUPUSU
分类号 G11C11/41;G11C8/16 主分类号 G11C11/41
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