Nonvolatile memory device capable of outputting correct read data at proper time.

摘要

A nonvolatile memory device has a memory cell (12) having its gate connected to a word line (WL), its source connected to a ground potential (Vss) and its drain connected to a power supply voltage (Vcc) via a bit line (BL) and a dummy cell (24) having its gate connected to the word line (WL), its source connected to the source potential and its drain connected to the power supply voltage (Vcc) via a dummy bit line (DBL). The bit line (BL) and the dummy bit line (DBL) are connected to reset and set terminals of a sense amplifier circuit (28) comprising a flip-flop circuit (30) and a latch type of sense amplifier (22). The conductance of the dummy cell (24) is made smaller than that of the memory cell (12) so that the speed at which the potential on the bit line (BL) is lowered depends on the state of injection of electrons into the memory cell (12) as compared with the speed at which the potential on the dummy bit line (DBL) at a time of reading data. The flip-flop circuit is reset or set in accordance with the speed at which (30) the potential on the bit line (BL) is lowered and then the latch type of sense amplifier (22) operates to latch the output of the flip-flop circuit (30) and output it as read data.