Digital computing system with low power mode.

摘要

An integrated circuit microcomputer (10) enters a low power mode in response to executing an LPSTOP instruction. Only reset events and those interrupt events having a priority level sufficiently high to pass an interrupt mask are capable of causing the termination of the low power mode. The LPSTOP instruction causes immediate data to be loaded into a status register, resetting the interrupt mask bits. The interrupt mask is then written, by means of a special bus cycle, into an interrupt mask register in a sub-system (16) within the microcomputer. This subsystem (16) then shuts down the clock signals to the remainder of the microcomputer (10), leaving only this sub-system (16) active. The active sub-system (16) performs a comparison of the priority levels of received interrupt requests to the interrupt mask during the low power mode.