| 摘要 |
PURPOSE:To test an existing logic region of a composite LSI by a method wherein a test pattern for an existing logic region is connected, and it is prepared before the start of the composite LSI design and given to the existing logic region of the composite LSI from the outside. CONSTITUTION:A half number of FFs 5-1, 5-2,...5-n, which are serially connected together as recording elements 5, are connected to an input terminal 6 of an existing logic region 4 and the rest are connected to an output terminal 7 of the region 4. Terminal pins Ack and Bck of a composite LSI denote input terminals of clocks of two phases, A and B, and a terminal pin Tck represents an input terminal of a test acting clock. when clocks are inputted into the FFs 5-1, 5-2,...5-n from the clock terminals respectively as shown by arrows and the composite LSI 1 starts operating normally, the recording elements 5 are not set to be as FF and the recording elements are not present from the standpoint of an external data terminal. And, when the existing logic region 4 is tested, a first bit of an operation test pattern is given to a terminal Sin of the existing logic region 4, and an initial clock is inputted into the recording element 5-1. |
