| 摘要 |
PURPOSE:To generate a difference signal with a few phase difference in a high speed operation by generating a positive phase signal from a cascade connection circuit comprising two stages of inverters receiving a single phase digital signal and generating, on the other hand, an negative phase signal with nearly equal delay time to that of two stages of the inverters with a source follower circuit and a negative phase signal generating circuit. CONSTITUTION:When a digital input signal with a periodic waveform enters an input terminal 1, a positive phase signal delayed by a delay time by two stages of CMOS inverter circuits with respect to the input signal is outputted to an output terminal 2. On the other hand, the input signal is inputted to a negative phase signal generating circuit simultaneously, the source level of the 1st NMOS transistor(TR) 13 rises at the leading of the input signal, the source level of the 1st PMOS TR 8 is descended, then a 2nd PMOS TR 10 and a 2nd NMOS TR 15 in series connection are driven and an inverted input signal appears at the output. Thus, a single phase input signal is converted into a difference signal with less phase difference without using a clock or a special circuit element. |
