| 摘要 |
<p>PURPOSE:To reduce memory capacity, to attain a high-speed operation, and to execute large-scale integration by latching a sub-decoded signal and after that executing the last decoding. CONSTITUTION:The n-bit address data are latched 1, the output bit of the latch 1 is passed through an inversion circuit 2, an adding circuit 3, and a clipping circuit 4, and while two data are inputted to a sub decoder 5, the other three data are inputted to a sub decoder 6, respectively. While the decoder 5 sends four outputs, the decoder 6 sends eight outputs. Further, the most significant bit of the output of the clipping circuit 4, the outputs of the decoder 5, the outputs of the decoder 6, and the most significant bit of the output of the inversion circuit 2 are respectively held in a latch 7, a latch 8, a latch 9, and a latch 10. The outputs of the decoders 5 and 6 are lastly decoded in a main decoder 11, and the address line of a memory 12 is driven by the output of the main decoder 11.</p> |
