| 摘要 |
The method includes forming in one surface of an N+ silicon wafer a matrix of uniformly deep V-shaped grooves, growing one SiO2 over the one surface and the walls of the grooves, forming over the opposite wafer surface a thick self-supporting polycrystalline layer, progressively removing portions of the original silicon wafer until the bottoms of the grooves are detected to leave separate patches of the original N+ silicon wafer material and then growing a thin (e.g. 6 microns) P-doped layer of epitaxial silicon on the exposed N+ silicon layer patch portions now isolated and defined by the grooves. A figure-eight pattern of trenches is formed in each silicon island completely through the P epitaxial layer and each of the underlying N+ buried patches but stopped at the SiO2 layer. An N+ plug is formed through the epitaxial layer to each N+ patch. Metal conductors complete the formation of a JFET transistor in each island bounded and defined by one of the closed loops or annular portions of the figure-eight-patterned trenches. The wafer is then sawed apart along all the V-shaped grooves providing a plurality of IC die, each having two dielectrically isolated JFET transistors.
|
