发明名称 FREQUENCY/PHASE LOCKED LOOP
摘要 PURPOSE:To decrease or evade the difference in the tracking characteristic at phase synchronizing operation and the tracking characteristic at frequency synchronizing operation by forming a PLL with a loop by a frequency comparator and a loop by a phase comparator. CONSTITUTION:The frequency comparator 11 is operated when an LKTSV signal is set, selects *INCf and *DECf signals generated from a frequency comparator 11 and supplies the 1st charge pump circuit 131. A phase comparator 12 is operated when the LKTDT signal is set, selects *INCp and *DECp signals generated from a phase comparator 12 to supply it to the 2nd charge pump circuit 132. When the output current characteristic of the 1st charge pump circuit 131 is set lower than the output current characteristic of the 2nd charge pump circuit 132, the tracking characteristic at the frequency synchronization slows down.
申请公布号 JPH02125528(A) 申请公布日期 1990.05.14
申请号 JP19880277426 申请日期 1988.11.04
申请人 FUJITSU LTD 发明人 TANAKA HIROYUKI;UNO KOJI
分类号 H03K5/26;H03L7/087;H03L7/093 主分类号 H03K5/26
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