| 摘要 |
PURPOSE:To lower an output signal to a low level within a prescribed time after an input signal is changed by providing a delay circuit retarding an input signal for a prescribed time, an AND circuit and the 2nd n-channel MOS TR connected in parallel with the 1st n-channel MOS TR. CONSTITUTION:The circuit consists of a 1st n-channel MOS transistor(TR) Qn1, a delay circuit 5, an AND circuit 6, and the 2nd n-channel MOS TR Qn2 using an output (c) of the circuit 6 and connected in parallel with the TR Qn1. In such a case, when an input signal I reaches an L level, the n-channel MOS TR Qn1 is energized, and an output (c) of the AND circuit 6 goes to an H level when the level of the output signal O is regarded as logical H even if nearly 10ns elapses after the p-channel MOS TR Qp1 is nonconductive, the n-channel MOS TR Qn2 is conductive thereby decreasing the level of the output signal O to the L level strongly. |
