| 摘要 |
PURPOSE:To reduce a circuit scale and to prevent a noise generation due to a control clock from being made into a problem by executing a large delay with a rough time quantization through the use of a first delaying means with a sampling to each reception and, thereafter, phasing and adding a small delay with a small time quantization through the use of a second delaying means. CONSTITUTION:Amplifier outputs 1, 2,-(n) from respective receiving elements are inputted to first delaying means SC-1, SC-2,-SC-n by sampling, respectively. Respective outputs of the first delaying means are current-converted by voltage/ current converters VI-1, VI-2,-VI-n and inputted to a switching means MPX with n-input and N-output. Respective input signals of the switching means are selectively connected to output terminals Q1, Q2,-QN of the switching means so as to execute the small delays corresponding to the delay quantities of respective receiving element by means of a control signal phiX from a control means. The switching means outputs are inputted to respective taps of a second delaying means DL to execute the small delay, current-added and, thereby, outputted to an output terminal Z-1 as a phasing output. As the second delaying means, for example, an analog LC delay line with a tap can be used. |
