| 摘要 |
The controller for adjusting phase difference between data signal and counterclock signal includes flip-flops (FF.,FF2) for converting control data to data with 16Kb/s utilizing clock signals having freguency of 64, 32, and 16 KHz multiplexers (U1,U2) for multiplexing data with 16Kb/s from a data converter (E1), a multiplexer (E2) for generating clock sigual, and a phase controller having flip-flops (FF15,FF16) for adjusting phase difference between input data (I4,- I7) and clock signal from the multiplexer (E2).
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