发明名称 BUFFER CIRCUIT
摘要 <p>PURPOSE:To obtain a buffer circuit outputting a logic signal with an optional time delay and controlling the delay time electrically by providing an exclusive OR circuit, an integration circuit, a voltage comparison circuit and a toggle type flip-flop circuit. CONSTITUTION:An output of an integration circuit 3 receiving an output of an exclusive OR circuit 2 is a reference value when an output of the exclusive OR circuit 2 is logical 0 and is an integration value of the output of the exclusive OR circuit 2 when the output of the exclusive OR circuit 2 is logical 1. A voltage comparator circuit 5 compares an output 9 of the integration circuit 3 with a signal potential at a control input terminal 4 to output logic 0 or 1 depending on the relation of quantity, and a toggle type flip-flop circuit 6 inverts the logic value of the output every time the output of the voltage comparator circuit 5 changes from logic 0 to logic 1 or vice versa and its output is connected to the input of the output terminal 7 and the input of the exclusive OR circuit 2. Thus, there is a time lag of T till the output of the output terminal 7 changes after the input at the input terminal 1 changes and the time T is controlled by a potential V4 of the control input terminal 4.</p>
申请公布号 JPH02124625(A) 申请公布日期 1990.05.11
申请号 JP19880278843 申请日期 1988.11.02
申请人 NEC CORP 发明人 SUGIMOTO MASUNORI
分类号 H03K5/13;H03K19/0175 主分类号 H03K5/13
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