| 摘要 |
PURPOSE:To improve the wiring containability by forming a conductor layer on the innerwall of a through-hole including a catalytic insulation layer formed with catalytic insulation substrate and a catalytic prepreg and catalyst adsorbing section through electroless plating thereby eliminating design restriction factor such as setting of characteristic impedance. CONSTITUTION:When a mask 8 is removed through organic solvent and electroless copper plating is applied, a conductor circuit pattern 1a of exposed multilayer substrate 6 and a conductor layer 10 on the inner wall of through- holes 7a, 7b are formed. In the through-hole 7a, the conductor layer 10 is formed only on a catalytic insulation layer 5 and not formed on the catalystless insulation substrate 3, and thereby the conductor layer 10 separates on the inner wall of the through-hole 7a and the conductor circuit patterns 1a, 1b are connected each other. In the through-hole 7b, the conductor layer 10 is formed entirely on the inner wall with the previously adsorbed catalyst 9. By such arrangement, a multilayer printed circuit board 13 containing splitted via-holed 11 and conventional through-hole 12 can be obtained. |
