发明名称 RAM TEST CIRCUIT
摘要 PURPOSE:To improve the function test efficiency without using many test terminals by reading the storage data received from a reference block and outputting them successively based on a prescribed shift clock. CONSTITUTION:In the case the same data are written into a reference block B0 and other memory blocks B1 and B2, a comparator 2 detects no discordance as long as both blocks B1 and B2 have no trouble. While the discordance is detected if one of both blocks B1 and B2 has a trouble. In the case the different data are written into the blocks B1 and B2, the comparison circuit 2 detects the discordance and therefore confirms the absence of troubles. The storage data of the block B0 are sequentially shifted by a shift register SR and outputted. This output signal is confirmed and then the function of the block BO is confirmed. Thus it is possible to improve the function test efficiency without using many test terminals.
申请公布号 JPH02121198(A) 申请公布日期 1990.05.09
申请号 JP19880272112 申请日期 1988.10.28
申请人 YAMAHA CORP 发明人 MURAMATSU TOSHIHIKO
分类号 G11C29/00;G06F11/22;G11C29/34 主分类号 G11C29/00
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