Sync detection circuit for phase-locked loop having frequency divider.

摘要

In a lock detection circuit, an input pulse signal at frequency f0 is compared with an output pulse signal from a frequency divider (5) to produce a control signal representative of a difference in frequency or phase between the input and output pulse signals. A voltage-controlled oscillator (4) generates pulses at a frequency f0 x N (where N >/= 2) when the control signal indicates that the frequency or phase difference is zero or pulses at a variable frequency when the control signal indicates that the frequency or phase difference is non-zero. The frequency divider (5) divides the frequency of the pulses from the oscillator (4) by a factor N to generate the output pulse signal. A decision circuit (6-11) is provided for detecting when the pulses generated by the oscillator (4) during an interval between pulses of the input pulse signal are equal to at least N to give an indication that a phase alignment is established between the input and output pulse signals. If N is equal to or greater than 4, the decision circuit (6-11) may comprise a frequency divider (12) for dividing the frequency of the input pulse signal by a factor M (where M >/= 2) to define the count interval between successive pulses from the second frequency divider (12), so that phase alignment occurs when MN pulses of the input pulse signal exist between the count interval.