| 摘要 |
A regulator circuit for equalizing the load currents of a plurality of power supply modules connected in common to feed a common load. Each of the modules includes a pulse-width modulator for adjusting the duty cycle of the module, thereby to adjust the voltage regulation point and corresponding current output of the module. A current sensor produces a current level signal proportional to the current output of the module. The current level signal is applied through a current amplifier to generate a corresponding variable error voltage. A fixed reference voltage derived from the output voltage and the variable error voltage are applied to the pulse-width modulator to vary the duty cycle so as to produce a decrease in load voltage with an increase in current output and an increase in the load voltage with a decrease in current output thereby equalizing the current output of the module with modules having substantially equal output voltages. A low pass filter interposed in the regulator feedback path assures current sharing under quasi steady-state conditions without degradation of high frequency response to dynamic load changes.
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