| 摘要 |
A two-port switched capacitor filter network of the type comprising two input terminals (4, 6), two output terminals (8, 10) and at least three integrator circuits (12, 14, 16) connected therebetween, each integrator circuit including two inputs provided with capacitors which are switched under the control of two disjoint clock states, said integrator circuits being interconnected to constitute a sampling filter having a selected amplitude/frequency response. The two-port network includes two other integrator circuits (36, 38) whose respective inputs are fitted with capacitors switched under the control of two disjoint clock states, said other integrator circuit being interconnected with each other and with the first-mentioned integrator circuits in order to linearize the phase/frequency response of said filter.
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