METHOD FOR THE MANUFACTURE OF COMPLEMENTARY MOS FIELD EFFECT TRANSISTORS IN VLSI TECHNOLOGY

摘要

The manufacture of n-channel and p-channel transistors in a CMOS process which involves employing gate spacer oxide layers for reducing the under-diffusion of the implanted sourcedrain regions under the gate areas. The spacer oxide widths for the n-channel and the p-channel transistor are set differently so that both transistor types can be optimized independently of one another and without an additional expenditure for more masking steps. The method is employed for the manufacture of large scale integrated circuits for fast switching speeds.