发明名称 TRI-STATE INVERTER
摘要 PURPOSE:To decrease the number of transistors(TRs) and to improve the area efficiency by constituting the inverter with 3 N-channel TRs and one p-channel TR in total four TRs. CONSTITUTION:With a High level inputted to an input terminal C, N-channel Trs N1, N3 are turned on, and with a High level inputted to an input terminal D at this time, then an N-channel Tr N2 is turned on and a P-channel Tr P1 is turned off, then a Low level is outputted to an output terminal O. Moreover, with a Low level inputted to the input terminal D, the N-channel TR N2 is turned off and the P-channel Tr P1 is turned on, then a High level is outputted to the output terminal O. With a Low level given to the input terminal C, then the N-channel Trs N1, N3 are turned off and the output terminal O is kept at a High impedance state independent of the state of the input terminal D at this time. Thus, the number of TRs is decreased.
申请公布号 JPH02119422(A) 申请公布日期 1990.05.07
申请号 JP19880273438 申请日期 1988.10.28
申请人 MATSUSHITA ELECTRIC IND CO LTD 发明人 TANAKA TETSUYA
分类号 H03K19/0175;H03K19/094 主分类号 H03K19/0175
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