摘要 |
<p>PURPOSE:To simultaneously execute data transfer and data processing by successively adding +1 to a counter in the title processor according to the data transfer, executing the data processing in the processor when a counter number is a positive number, and inhibiting the data processing when the counter number is zero. CONSTITUTION:When prescribed instruction data are inputted to an instruction register 4, an instruction decoder 5 decodes the data and adds -1 to an up/down counter 1 according to the decoded result. Further, a bus control interface circuit 6 is accelerated its task of data processing until a zero output is obtained in a zero detecting circuit 2. When the value of the counter 1 goes to '0', the output of the circuit 2 comes to true, and an interruption signal is generated according to the contents of a flag register 3, starts interruption control for the circuit 6, and inhibits the data processing of the processor. In the same manner, the interruption signal generated according to the contents of the register 3 is outputted to the external part of the processor, starts interruption control for the processor from the external part, and inhibits the prescribed data processing.</p> |