| 摘要 |
<p>PURPOSE:To attain the easy time step-out detection of control by providing parity data generation circuits with the contents of all the counters and exclusive OR circuits inputting the outputs of the parity data generation circuits. CONSTITUTION:The parity data generation circuits 13 and 23 with all the bits of the time counters 11 and 21 are provided, and parity data of one bit in the circuits are outputted to signal lines 4 and 5. Then, the exclusive OR circuits 14 and 24 for comparing the outputs of the parity data generation circuits 13 and 23 on the signal lines 4 and 5 are provided. When the outputs of the parity data generation circuits 13 and 23 in respective processors differ, the outputs of the exclusive OR circuits 14 and 24 come to '1', and time-step out is detected. Thus, step-out between the processors can be detected by simple constitution by comparing the contents of all the counters in multi-processor systems 1 and 2 where plural clock counters 11 and 12 exist.</p> |
