| 摘要 |
<p>PURPOSE:To halve each circuit scale of a memory and an address decoder by storing only a data of one state into the memory and making the data correspondent to an address signal from the address decoder one by one. CONSTITUTION:An address signal in the relation in address signals corresponding to an input data from an address decoder AD1 having a relation of inverted or equal state while the content of an output data corresponding to a memory 2 is between one state and other state, is inputted to the memory 2, and an address signal having no relation is inputted to memory 2 and an AND circuit 5. The memory 2 outputs an output data of one state and its disparity signal corresponding to the input address signal. An inverter 3 uses an output signal of a register 4 to decide the presence of inversion and outputs a data. Then an inverter 6 is controlled by an AND output between the address signal from the AD1 and the disparity signal from the register 4. The output data consists of each output from the inverters 3, 6.</p> |
